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NASDAQ, CDNS: Cadence Design Sys

26 Jan 26 14:45
LAST:

322.1

CHANGE:
 3.83
OPEN:
316.8
HIGH:
323.6
ASK:
39.1
VOLUME:
419.1K
CHG(%):
1.20
PREV:
318.2
LOW:
314.1
BID:
28.5
 

CHART

RECENT END OF DAY PRICES

DateOpenHighLowCloseVolume
26 Jan 26316.8323.6314.1322.1419.1K
23 Jan 26315.5323.5312.0318.31.47M
22 Jan 26317.0317.8310.8317.11.38M
21 Jan 26307.5316.2305.0313.81.72M
20 Jan 26310.6311.5305.8307.02.04M
16 Jan 26321.8322.5314.5317.52.09M
15 Jan 26317.4328.6316.0320.62.4M
14 Jan 26319.5320.5309.9313.22.04M
13 Jan 26322.6327.7318.0323.11.2M
12 Jan 26325.9328.5321.0325.51.49M

PROFILE

Name:Cadence Design Sys
About:Cadence Design Systems, Inc. provides software, hardware, and other services worldwide. The company offers functional verification services, such as Jasper, a formal verification platform; Xcelium, a parallel logic simulation platform; Palladium, an enterprise emulation platform; and Protium, a prototyping platform for chip verification. It also provides digital IC design and sign off products, including Genus synthesis and Joules RTL power solutions, as well as Modus DFT software solution to reduce systems-on-chip design-for-test time; physical implementation tools, such as place and route, optimization, and performing sign-off checks for manufacturing; and Innovus implementation system, a digital IC design and signoff solution. In addition, the company offers custom IC design and simulation, such as Virtuoso Studio, a solution platform for custom, analog, mixed-signal, photonics, and RF semiconductors; and system design and analysis products, a Multiphysics platform that helps in design and simulate electronics and entire systems in electromagnetic, thermal, structure, computational fluid dynamics, molecular, PCB and packaging, mechanical, and structural analysis. Further, it provides semiconductor IP product for design architectures; Functional Verification; digital ic design and signoff; EDA product that addresses the design and verification for semiconductor chips and manufacturing process technologies; and verification IP with memory models to emulate and model the expected behavior and interaction of standard industry system interface protocols. Additionally, it offers services related to methodology, education, and hosted design solutions, as well as technical support and maintenance services. It serves consumer, hyperscale computing, 5G communications, mobile, automotive, aerospace and defense, industrial, and life science industries. Cadence Design Systems, Inc. was incorporated in 1987 and is headquartered in San Jose, California.
Sector:Technology
Address:Building 5, San Jose, CA, United States, 95134
Website:https://www.cadence.com
CUSIP:127387108
CIK:0000813672
ISIN:US1273871087
FIGI:BBG000C13CD9
LEI:GCT7RXJOGLXPV0NXZY22

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FUNDAMENTALS

Trailing P/E:81.36 
Forward P/E:39.81 
PEG Ratio:-2.85 
Price to Sales:17.69 
Price to Book:16.78 
Profit Margin:0.20 
Operating Margin:0.35 
Return on Assets:0.11 
Return on Equity:0.22 
EPS Ratio:3.94 
Revenue:5.213B 
EBITDA:1.876B 
Shares:272.2M 
Market Cap:87.666B 

TECHNICAL INDICATORS

MA5:315.652.0%
MA10:317.811.3%
MA20:316.791.7%
MA50:317.461.4%
MA100:330.452.6%
MA200:323.110.3%
STO9:69.41
STO14:69.41
RSI14:63.04 
WPR14:-26.05
MTM14:7.38
ROC14:0.02 
ATR:10.79 
Week High:323.630.5%
Week Low:304.955.6%
Month High:328.642.0%
Month Low:300.400.3%
Year High:376.4516.9%
Year Low:221.5645.4%
Volatility:13.40 

RECENT SPLITS

Date Ratio
17 Nov 19972-1
03 Jun 19963-2
31 Oct 19953-2